1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same semiconductor device.
2. Description of the Prior Art
The manufacturing process of a conventional semiconductor device having a capacitor will be explained hereinbelow with reference to FIGS. 13A to 13C, FIGS. 14A to 14C and FIGS. 15A to 15C.
First, as shown in FIG. 13A, an element separating region 52 is formed on a semiconductor substrate 51 by LOCOS (Local Oxidization of Silicon), for instance. Further, as shown in FIG. 13B, a poly-crystal silicon film 53 having a film thickness of about 200 nm is formed on the element separating region 52 by LPCVD (Low-Pressure Chemical Vapor Deposition), and then the formed poly-crystal silicon film 53 is patterned by anisotropic etching method, for instance such as reactive ion etching (referred to as RIE, hereinafter). After that, as shown in FIG. 13C, a silicon oxide film 55 having a film thickness of about 500 nm is deposited on the substrate as an interlayer insulating film by CVD (Chemical Vapor deposition) method, for instance.
Further, as shown in FIG. 14A, the silicon oxide film 55 formed at a capacitor forming region is removed to open a hole 57 by the RIE method, for instance. After that, as shown in FIG. 14B, a silicon nitride film 59 having a film thickness of about 50 nm is deposited all over the substrate as a capacitor insulating film. Successively, as shown in FIG. 14C, the silicon nitride film 59 is removed from the area other than the capacitor forming region.
Further, as shown in FIG. 15A, a contact hole 63 is opened in the silicon oxide film 55 by the RIE method. Successively, as shown in FIG. 15B, an Al wiring film 61 containing silicon of lat % (for instance) is deposited by sputtering, for instance. Further, as shown in FIG. 15C, two wiring portions 61a and 61b are formed by patterning the Al wiring film 61, and then sintered within a forming gas atmosphere at 450.degree. C. After that, a silicon oxide film (not shown) having a film thickness of about 1000 nm, for instance is formed on the surface of the substrate as a passivation film.
Here, the component of the forming gas is hydrogen diluted by nitrogen, and the hydrogen concentration thereof is about 10 to 30%. The substrate is sintered for two objects as follows: One is to improve the electrical contact between the wire (Al or barrier metal) and the underground silicon, and the other is to terminate an excessive potential level in the interface between the gate insulating film and the silicon.
In the conventional semiconductor device as described above, however, the Al wiring film 61 is formed by the sputtering on condition that the capacitor insulating film 59 is left exposed. In this case, prior to the sputtering, when Ar ions are sputtered (referred to as sputtering, hereinafter) in order to remove a natural oxide film formed on the bottom of the contact hole 63, since the capacitor insulating film 59 is also exposed for the sputtering, the insulating film 59 is inevitably cut down, so that there exists a problem in that the controllability of the capacitance of the capacitor deteriorates.
In addition, although not shown in the above-mentioned conventional semiconductor device, when tungsten, for instance is electively grown to bury the contact hole 63, since the tungsten is grown in the same way when the capacitor insulating film is left exposed, tungsten is inevitably grown on the capacitor insulating film. Further, when the excessive tungsten is peeled off by sputtering, since the capacitor insulating film is exposed to etching, there exists a problem in that the film thickness also disperses.
The manufacturing process of a conventional analog LSI used for mobil communications will be explained hereinbelow with reference to FIGS. 26A to 26C, FIGS. 27A to 27C, FIGS. 28A to 28C, and FIGS. 29A and 29B. Here, this analog LSI is formed with a bipolar transistor, a MOS type field effect transistor (referred to as MOSFET, hereinafter), and a capacitor.
First, as shown in FIG. 26A, after an oxide film 172 has been formed on a silicon substrate 171 by thermal oxidization, the formed oxide film 172 is patterned by etching with the use of photolithography and HF based solution, to remove the oxide film 172 from a region where a buried layer is to be formed. Successively, after a glass layer 173 containing Sb has been formed all over the surface of the silicon substrate 171, Sb is diffused in the silicon substrate by thermal process, to form an N.sup.+ buried layer 174.
Further, as shown in FIG. 26B, after the glass layer 173 has been removed and further the oxide film 172 has been peeled off by use of the HF based solution, a monocrystal silicon layer 175 containing phosphorous of 3.0.times.10.sup.16 cm.sup.-3 is formed all over the substrate by epitaxial growth method.
Successively, as shown in FIG. 26C, after the substrate surface has been oxidized to form an oxide film 176 having a film thickness of about 500 .ANG., a poly-crystal silicon layer 177 having a film thickness of about 1000 .ANG. and a silicon nitride film 178 having a film thickness of about 1500 .ANG. are both deposited in sequence. Further, the silicon nitride film 178 and the poly-crystal silicon film 177 are both removed, by use of the photolithography and the RIE (Reactive-Ion Etching), from the regions where element separating regions are to be formed.
Successively, as shown in FIG. 27A, an element separating oxide film 179 is formed on the regions from which the silicon nitride film 178 and the poly-crystal silicon film 177 have been already removed. Successively, the silicon nitride film 178 and the poly-crystal silicon film 177 remaining on the substrate are both removed by CDE (Chemical Dry Etching) method.
Further, as shown in FIG. 27B, a P well 180 and an N well 181 are formed at regions where the MOSFET is to be formed by use of the photolithography and ion implanting technique. Successively, channels are formed by ion implantation. Further, after a oxide film 176 formed on the element region has been removed, a gate oxide film 184 is formed by the thermal oxidization. Further, a poly-crystal silicon having a film thickness of about 3000 .ANG. has been deposited all over the substrate surface, the substrate is patterned to form a gate electrode 185. After that, an N-type diffusion layer 182 and a P-type diffusion layer 183 are formed by the photolithography and the ion implantation technique.
Further, as shown in FIG. 27C, after a silicon oxide film 188 having a film thickness of about 3000 .ANG. has been deposited all over the substrate surface by the LPCVD method, the silicon oxide film 188 formed on the region where a bipolar transistor is to be formed is removed by patterning with the use of the photolithography and the wet etching of HF based solution, to expose the monocrystal silicon layer 175 and the element separating oxide film 179 formed on the silicon substrate 171.
Further, as shown in FIG. 28A, the monocrystal silicon layer 190a or 190b containing P-type impurities (e.g., boron) is formed on the exposed monocrystal silicon layer 175 by use of the selective epitaxial technique. After that, a silicon oxide film is deposited all over the substrate surface, to form an etching stopper film 192 remaining on the region where a base region is to be formed by patterning this silicon oxide film.
Further, as shown in FIG. 28B, a poly-crystal silicon film has been deposited all over the substrate surface, a base leading electrode 194a and a collector leading electrode 194b are formed by patterning. Further, the P-type impurities are implanted at the base leading electrode 194a and the N-type impurities are implanted at the collector leading electrode 194b, respectively. In this process, since the N-type impurities are implanted in the P-type monocrystal silicon layer 190b formed under the collector leading electrode 194b, the P-type monocrystal silicon layer 190b is reversed into the N-type. After that, a silicon nitride film 196 is deposited on the bipolar transistor forming region by use of the CVD (Chemical Vapor Deposition). Successively, the silicon nitride film 196 and the poly-crystal silicon film 194a formed on the etching stopper film 192 are both removed by use of the RIE method, to form a hole 197 for forming an emitter region.
Successively, as shown in FIG. 28C, a nitride film is deposited all over the substrate surface by use of the CVD method, and a side wall 198 is formed on a side surface of the hole 197 by the RIE. Further, the etching stopper film 192 is etched by use of the wet etching with the formed side wall 198 as a mask, to expose the monocrystal silicon layer 190a, without damaging the monocrystal silicon layer 190a used as the base region. Further, after the poly-crystal silicon layer has been deposited all over the substrate surface, N-type impurities have been implanted in the poly-crystal silicon layer, and further an emitter region 202 is formed in the base region 190a by thermal process. After that, the poly-crystal silicon layer containing N-type impurities is patterned to form an emitter electrode 200 at the bipolar transistor region and a lower capacitor electrode 201 at the MOSFET forming region.
Further, as shown in FIG. 29A, a silicon oxide film having a film thickness of about 8000 .ANG. is deposited all over the substrate surface by use of the LPCVD method, to form an interlayer insulating film 209 to be formed under a first-layer Al wire. Further, after a hole has been opened in the interlayer insulating film 209 formed on the lower capacitor electrode 201, a silicon nitride film has been deposited and further the deposited silicon nitride film is patterned, to form a dielectric insulating film 210.
Further, as shown in FIG. 29B, after various contact holes for the respective electrodes of the bipolar transistor, the MOSFET and the lower capacitor electrode 201 have been opened in the interlayer insulating film 209, a natural oxide film formed at the bottoms of the contact holes is removed by use of the HF based solution. Further, after that, a barrier metal layer formed of Ti/TiN for instance has been deposited at the bottoms of the contact holes by use of the sputtering in order to prevent Al from being diffused to the silicon substrate, a metal wire layer formed of Al--Si--Cu alloy, for instance is deposited by use of the sputtering method. Further, the substrate is patterned to form the respective wires 214 connected to the respective electrodes of the bipolar transistor and the MOSFET and the lower capacitor electrode 201. In addition, an upper capacitor electrode 115 is also formed, with the result that a desired circuit can be completed.
The conventional circuit formed as described above can be used as the analog LSI of high performance. Here, however, there exist the following problems.
In order to further improve the performance, the case will be considered where the poly silicon electrodes (the emitter electrode 200, the base leading electrode 194a, and the collector leading electrode 194b) of the bipolar transistor, the poly silicon electrode (the gate electrode 185) of the MOSFET and the lower capacitor electrode 201 are all silicided into metals, respectively. In this case, since the silicide (e.g., TiSi.sub.2, CoSi, etc.) is soluble in the HF based solution used for the ordinary LSI process, it is impossible to use the HF based solution when the natural oxide film formed on the silicide at the bottoms of the contact holes are required to be removed. To remove the natural oxide film formed on the silicide, it is necessary to use the dry etching such as Ar sputtering. In this case, however, when the natural oxide film formed on the silicide is being removed by the Ar sputtering, the dielectric insulating film 210 for constructing the capacitor is also inevitably cut down. As a result, there exists a problem in that the controllability of the capacitance of the capacitor is degraded, and thereby the reliability of the capacitor deteriorates markedly.
This has been clarified on the basis of the TDDB (Time Depend Dielectric Breakdown) test results obtained by the inventors. In this TDDB test, a plurality of capacitors each having a dielectric film formed of silicon nitride and a film thickness of about 500 .ANG. (which has been further sputtered by Ar) are prepared. Further, the times until the capacitors are broken down are measured, on condition that the high voltages (e.g., three voltages of 32.5 V, 35 V, 37.5 V) are applied to these capacitors. FIG. 30 shows the test results, in which the breakdown time is expressed on the abscissa in logarithmic scale and the Weibull values are shown on the ordinate. Here, the Weibull values can be obtained on the basis of the survival probability of the sample population. Further, the Weibull values are so selected as to satisfy the linear relationship with respect to the logarithmic values of the breakdown times of the respective samples, as far as the sample population is normal. FIG. 30 indicates that the gradients of the Weibull lines at the respective voltages are different from each other and thereby the Weibull lines cross each other. This indicates that the capacitor reliability deteriorates.